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utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description released date preliminary rev. 0.5 1. original. mar, 2001 rev. 1.0 1. the symbols ce# and oe# and we# are revised as. ce and oe and we . 2. separate industrial and commercial spec. 3. add access time 55ns range. jun 21, 2001 rev. 1.1 1. the extended temperat ure range is revised. -20 j ~80 j b -20 j ~85 j aug 24, 2001 rev. 1.2 1. revised power supply a ?b 55ns (max.) for vcc=2.7v~3.6v b ?b 70/100ns (max.) for vcc=2.5v~3.6v 2. revised block diagram 3. revised dc electrical characteristics ?g a ?b revised v ih as 2.2v b ?b revised standby current i sb1 of ll-version typical : 3ua b 2ua maximum : 25ua b 20ua 4. revised ac electrical characteristics ?g c ?b revised symbol name t hzb as t bhz d ?b revised symbol name t lzb as t blz e ?b revised symbol name t pwb as t bw f ?b revised t blz as 10ns (min.) g ?b revised t oh as 10ns (min.) 5. revised waveforms 6. revised 48-pin tfbga package outline dimension ?g h ?b rev. 1.1 ball diameter=0.3mm i ?b rev. 1.2 ball diameter=0.35mm apr 15, 2002 rev. 1.3 order information : add 100ns parts aug 05, 2002 rev. 1.4 add order information for lead free product may 09, 2003
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? features fast access time : 55ns (max.) for vcc=2.7v~3.6v 70/100ns (max.) for vcc=2.5v~3.6v cmos low power operating operating current : 45/35/25ma (icc max.) standby current : 20ua (typ.) l-version 2ua (typ.) ll-version single 2.5v~3.6v power supply operating temperature : commercial : 0 j ~70 j extended : -20 j ~85 j all ttl compatible inputs and outputs fully static operation three state outputs data retention voltage : 1.5v (min.) data byte control : lb (i/o1~i/o8) ub (i/o9~i/o16) package : 44-pin 400mil tsop- o 48-pin 6mm 8mm tfbga general description the ut62l12816 is a 2,097,152-bit low power cmos static random access memory organized as 131,072 words by 16 bits. the ut62l12816 operates from a single 2.5v~3.6v power supply and all inputs and outputs are fully ttl compatible. the ut62l12816 is designed for low power system applications. functional block diagram decoder i/o data circuit control circuit 128k ?? 16 memory array column i/o ce oe we a0-a16 vcc vss i/o1-i/o8 lower byte i/o9-i/o16 upper byte ub lb
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? pin configuration a1 a2 a3 a4 i/o16 i/o1 i/o2 i/o3 vcc vss nc a16 i/o15 i/o13 i/o14 i/o12 vss vcc i/o11 i/o10 i/o4 i/o5 tsop ii 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a15 a0 i/o7 i/o8 a5 a6 a7 a8 a9 i/o6 i/o9 a14 a13 a12 a10 nc 34 29 30 31 32 33 44 39 40 41 42 43 35 36 37 38 a11 ce we lb ub oe lb a0 oe a1 nc a2 i/o9 a3 ub a4 i/o1 ce i/o10 a5 i/o11 a6 i/o3 i/o2 vss nc i/o12 a7 vcc i/o4 vcc nc i/o13 a16 vss i/o5 i/o15 a14 i/o14 a15 i/o7 i/o6 i/o16 a12 nc a13 i/o8 we nc a9 a8 a10 nc a11 123456 h g c d e f a b tfbga pin description symbol description a0 - a16 address inputs i/o1 - i/o16 data inputs/outputs ce chip enable input we write enable input oe output enable input lb lower byte control ub upper byte control v cc power supply v ss ground nc no connection
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? truth table i/o operation mode ce oe we lb ub i/o1-i/o8 i/o9-i/o16 supply current standby h x x x x x x h x h high ? z high ? z high ? z high ? z i sb , i sb1 output disable l l h h h h l x x l high ? z high ? z high ? z high ? z i cc ,i cc1 ,i cc2 read l l l l l l h h h l h l h l l d out high ? z d out high ? z d out d out i cc ,i cc1 ,i cc2 write l l l x x x l l l l h l h l l d in high ? z d in high ? z d in d in i cc ,i cc1 ,i cc2 note: h = v ih , l=v il , x = don't care. absolute maximum ratings * parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 4.6 v commercial t a 0 to 70 j operating temperature extended t a -20 to 85 j storage temperature t stg -65 to +150 j power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 secs) tsolder 260 j *stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other co nditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity. dc electrical characteristics (v cc = 2.5v~3.6v, t a = 0 j to 70 j / -20 j to 85 j (e)) parameter symbol test condition min. typ. max. unit 55 2.7 3.0 3.6 v power voltage v cc 70/100 2.5 -- 3.6 v input high voltage v ih *1 2.2 - v cc +0.3 v input low voltage v il *2 -0.2 - 0.6 v input leakage current i li v ss ?? v in ?? v cc - 1 - 1 a output leakage current i lo v ss ?? v i/o ?? v cc; output disable - 1 - 1 a output high voltage v oh i oh = -1ma 2.2 - - v output low voltage v ol i ol = 2.1ma - - 0.4 v 55 - 30 45 ma 70 - 25 35 ma operating power supply current i cc cycle time=min, 100%duty i i/o =0ma, ce =v il 100 - 20 25 ma icc1 tcycle= 1 s - 4 5 ma average operation current icc2 100%duty, i i/o= 0ma ce ?? 0.2v, other pins at 0.2v or vcc-0.2v tcycle= 500ns - 8 10 ma standby current (ttl) i sb ce =v ih, other pins =v il or v ih - 0.3 0.5 ma -l - 20 80 a standby current (cmos) i sb1 ce =v cc -0.2v other pins at 0.2v or vcc-0.2v -ll - 2 20 a notes: 1. overshoot : vcc+3.0v for pulse width less than 10ns. 2. undershoot : vss-3.0v fo r pulse width less than 10ns. 3. overshoot and undershoot ar e sampled, not 100% tested.
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? capacitance (t a =25 j , f=1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0v to 3.0v input rise and fall times 5ns input and output timing reference levels 1.5v output load c l = 30pf, i oh /i ol = -1ma/2.1ma ac electrical characteristics ( t a =0 j to 70 j / -20 j to 85 j (e)) (1) read cycle ut62l12816-55 v cc =2.7v~3.6v ut62l12816-70 v cc =2.5v~3.6v ut62l12816-100 v cc =2.5v~3.6v parameter symbol min. max. min. max. min. max. unit read cycle time t rc 55 - 70 - 100 - ns address access time t aa - 55 - 70 - 100 ns chip enable access time t ace - 55 - 70 - 100 ns output enable access time t oe - 30 - 35 - 50 ns chip enable to output in low z t clz* 10 - 10 - 10 - ns output enable to output in low z t olz* 5 - 5 - 5 - ns chip disable to output in high z t chz* - 20 - 25 - 30 ns output disable to output in high z t ohz* - 20 - 25 - 30 ns output hold from address change t oh 10 - 10 - 10 - ns lb , ub access time t ba - 55 - 70 - 100 ns lb , ub to high-z output t bhz - 25 - 30 - 40 ns lb , ub to low-z output t blz 10 - 10 - 10 - ns (2) write cycle ut62l12816-55 v cc =2.7v~3.6v ut62l12816-70 v cc =2.5v~3.6v ut62l12816-100 v cc =2.5v~3.6v parameter symbol min. max. min. max. min. max. unit write cycle time t wc 55 - 70 - 100 - ns address valid to end of write t aw 50 - 60 - 80 - ns chip enable to end of write t cw 50 - 60 - 80 - ns address set-up time t as 0 - 0 - 0 - ns write pulse width t wp 45 - 55 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns data to write time overlap t dw 25 - 30 - 40 - ns data hold from end of write time t dh 0 - 0 - 0 - ns output active from end of write t ow* 5 - 5 - 5 - ns write to output in high z t whz* - 30 - 30 - 40 ns lb , ub valid to end of write t bw 45 - 60 - 80 - ns *these parameters are guaranteed by device char acterization, but not production tested.
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? timing waveforms read cycle 1 (address controlled) (1,2) t rc t aa data valid address dout t oh t oh previous data valid read cycle 2 ( ce and oe controlled) (1,3,4,5) t rc t aa t ace t blz t oe t ohz t clz t bhz t oh t olz high-z data valid high-z t ba t chz address dout ce lb , ub oe notes : 1. we is high for read cycle. 2.device is continuously selected oe =low, ce =low, lb or ub =low . 3.address must be valid prior to or coincident with ce =low , lb or ub =low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz , t olz , t chz , t bhz and t ohz are specified with c l =5pf. transition is measured ? 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz .
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? write cycle 1 ( we controlled) (1,2,3,5,6) t wc t aw t cw t as t wp t bw t whz t ow t wr high-z (4) (4) address ce we lb , ub dout din data valid t dw t dh write cycle 2 ( ce controlled) (1,2,5,6) t wc t aw t cw t as t wr t wp t bw t whz t dw t dh data valid high-z (4) address ce we lb , ub dout din
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? write cycle 3 ( lb , ub controlled) (1,2,5,6) t wc t aw t as t wr t cw t wp t bw t whz t dw t dh data valid address ce we lb , ub dout din high-z notes : 1. we , ce , lb , ub must be high during all address transitions. 2.a write occurs during the overlap of a low ce , low we , lb or ub =low. 3.during a we controlled write cycle with oe low, t wp must be greater than t whz +t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce , lb , ub low transition occurs simultaneously with or after we low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured ? 500mv from steady state.
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? data retention characteristics (t a = 0 j to 70 j / -20 j to 85 j (e)) parameter symbol test condition min. typ. max. unit vcc for data retention v dr ce ? v cc -0.2v 1.5 - 3.6 v - l - 1 50 a data retention current i dr vcc=1.5v ce ? v cc -0.2v - ll - 0.5 20 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ms recovery time t r 5 - - ms data retention waveform low vcc data retention waveform (1) ( ce controlled) v dr ? 1.5v ce ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr ce low vcc data retention waveform (2) ( lb , ub controlled) v dr ? 1.5v lb,ub ? v cc -0.2v v cc(min.) v cc(min.) v ih v ih v cc t r t cdr lb,ub
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? package outline dimension 44-pin 400mil tsop- o package outline dimension c dimensions in millmeters dimensions in inchs symbols min. nom. max. min. nom. max. a 1.00 - 1.20 0.039 - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.95 1.00 1. 05 0.037 0.039 0.041 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.12 - 0.21 0.0047 - 0.083 d 18.313 18.415 18.517 0.721 0.725 0.728 e 11.854 11.836 11 .838 0.460 0.466 0.470 e1 10.058 10.180 10. 282 0.398 0.400 0.404 e - 0.800 - - 0.0315 - l 0.40 0.50 0.60 0.0157 0.020 0.0236 2d - 0.805 - - 0.0317 - y 0.00 - 0.076 0.000 - 0.003 k 0 o - 5 o 0 o - 5 o
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? 48-pin 6mm 8mm tfbga package outline dimension
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? ordering information commercial temperature part no. access time (ns) standby current (a) typ. package ut62l12816mc-55l 55 20 44 pin tsop- o ut62l12816mc-55ll 55 2 44 pin tsop- o ut62l12816mc-70l 70 20 44 pin tsop- o ut62l12816mc-70ll 70 2 44 pin tsop- o ut62l12816mc-100l 100 20 44 pin tsop- o ut62l12816mc-100ll 100 2 44 pin tsop- o ut62l12816bs-55l 55 20 48 pin tfbga ut62l12816bs-55ll 55 2 48 pin tfbga ut62l12816bs-70l 70 20 48 pin tfbga ut62l12816bs-70ll 70 2 48 pin tfbga ut62l12816bs-100l 100 20 48 pin tfbga ut62l12816bs-100ll 100 2 48 pin tfbga extended temperature part no. access time (ns) standby current (a) typ. package ut62l12816mc-55le 55 20 44 pin tsop- o ut62l12816mc-55lle 55 2 44 pin tsop- o ut62l12816mc-70le 70 20 44 pin tsop- o ut62l12816mc-70lle 70 2 44 pin tsop- o ut62l12816mc-100le 100 20 44 pin tsop- o ut62l12816mc-100lle 100 2 44 pin tsop- o ut62l12816bs-55le 55 20 48 pin tfbga ut62l12816bs-55lle 55 2 48 pin tfbga ut62l12816bs-70le 70 20 48 pin tfbga ut62l12816bs-70lle 70 2 48 pin tfbga ut62l12816bs-100le 100 20 48 pin tfbga ut62l12816bs-100lle 100 2 48 pin tfbga
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? ordering information (for lead free product) commercial temperature part no. access time (ns) standby current (a) typ. package ut62l12816mcl-55l 55 20 44 pin tsop- o ut62l12816mcl-55ll 55 2 44 pin tsop- o ut62l12816mcl-70l 70 20 44 pin tsop- o ut62l12816mcl-70ll 70 2 44 pin tsop- o ut62l12816mcl-100l 100 20 44 pin tsop- o ut62l12816mcl-100ll 100 2 44 pin tsop- o ut62l12816bsl-55l 55 20 48 pin tfbga ut62l12816bsl-55ll 55 2 48 pin tfbga ut62l12816bsl-70l 70 20 48 pin tfbga ut62l12816bsl-70ll 70 2 48 pin tfbga ut62l12816bsl-100l 100 20 48 pin tfbga ut62l12816bsl-100ll 100 2 48 pin tfbga extended temperature part no. access time (ns) standby current (a) typ. package ut62l12816mcl-55le 55 20 44 pin tsop- o ut62l12816mcl-55lle 55 2 44 pin tsop- o ut62l12816mcl-70le 70 20 44 pin tsop- o ut62l12816mcl-70lle 70 2 44 pin tsop- o ut62l12816mcl-100le 100 20 44 pin tsop- o ut62l12816mcl-100lle 100 2 44 pin tsop- o ut62l12816bsl-55le 55 20 48 pin tfbga ut62l12816bsl-55lle 55 2 48 pin tfbga ut62l12816bsl-70le 70 20 48 pin tfbga ut62l12816bsl-70lle 70 2 48 pin tfbga ut62l12816bsl-100le 100 20 48 pin tfbga ut62l12816bsl-100lle 100 2 48 pin tfbga
utron ut62l12816 rev. 1.4 128k x 16 bit low power cmos sram utron technology inc. p80050 1f, no. 11, r&d rd. ii, science-based industr ial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 14 ? this page is left blank intentionally.

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